I2C is a committee. SPI is a dictatorship.

UART means Universal Asynchronous Receiver/Transmitter.

Unlike USB, this interface is effectively everywhere in PC-class hardware. Desktops and servers still carry UART through the old Super I/O bureaucracy, usually a chip from the lineage discussed in Nuvoton: The Chip Nobody Sees.

UART is a private phone call on a bad line.

Two sides agree on the speed beforehand, then trust each other not to drift too far from reality. There is no clock wire. There is no addressing. There is no bus arbitration. There is only a transmit line, a receive line, and faith in the oscillator.

This should have died with beige towers and DB-9 connectors.

It did not.

The Supreme Leader still finds UART in boot loaders, kernel consoles, BMC redirection paths, microcontrollers, GPS modules, Bluetooth chips, baseband debug ports, router headers, and development boards that claim to be modern while exposing yesterday’s electrical shame on a 0.1-inch pin header.

Because when everything else fails, engineers still want one thing:

a text stream that talks before the system is fully alive.

I. The Idea

It is not a bus in the grand political sense. It is a hardware block that converts between:

• parallel bytes inside a machine
• serial bits on a wire

The key word is asynchronous. Unlike SPI or I2C, UART sends no separate clock. Both ends prearrange the bit rate and framing format, then sample based on their own local clocks.

This is primitive. It is also efficient.

No clock line means fewer wires. Fewer wires means longer survival.

II. The PC Lineage

The IBM PC turned UART into state infrastructure.

Early PCs used the 8250 family. Then came the 16450. Then the 16550, whose original implementation famously shipped with broken FIFOs. The corrected 16550A became the model the rest of the industry copied for the next several decades.

Part	Era	What mattered
8250	early PC period	basic UART, one-byte buffering
16450	AT era	faster implementation, still shallow buffering
16550	late 1980s	intended FIFO design, original revision flawed
16550A	the one that mattered	16-byte FIFOs, canonical PC serial behavior

The Supreme Leader respects a part that became immortal by fixing one embarrassing mistake and then never leaving the board diagrams.

III. The Frame

UART communication is built from frames.

The line sits idle at logic high. A byte begins with a start bit driven low. Then come the data bits, usually least significant bit first. Then optionally a parity bit. Then one or more stop bits at logic high.

The most famous format is 8N1:

• 8 data bits
• no parity
• 1 stop bit

idle  start   b0 b1 b2 b3 b4 b5 b6 b7   stop
 1      0      d0 d1 d2 d3 d4 d5 d6 d7    1

If both sides agree on 115200 8N1, the receiver watches for the falling edge of the start bit, then samples the line near the middle of each expected bit interval.

This is why clock accuracy matters. UART is built on the assumption that neither side lies too much about time.

IV. Baud Rate: Trust, But Sample Carefully

Common UART speeds are a museum of accumulated habit:

Baud	Where you still see it
9600	industrial devices, GPS modules, conservative defaults
19200	legacy serial gear
38400	older modems, embedded defaults
57600	mid-speed console work
115200	standard modern debug console
921600 and above	fast embedded links when both sides behave

Historically, PC UARTs derived these rates from a 1.8432 MHz reference clock because it divided neatly into the standard baud table.

The classic divisor formula is:

baud = input_clock / (16 * divisor)

For 115200, a UART using a 1.8432 MHz clock sets the divisor to 1.

For 9600, it sets the divisor to 12.

The Supreme Leader approves of any subsystem where arithmetic replaces negotiation.

V. The Register Block Everybody Learned

The 16550-compatible programming model became the civil code of serial ports:

Register	Purpose
RBR / THR	receive buffer / transmit holding
IER	interrupt enable
IIR / FCR	interrupt identification / FIFO control
LCR	line control: word length, parity, stop bits
MCR	modem control
LSR	line status: data ready, transmitter empty, errors
MSR	modem status
DLL / DLM	divisor latch low/high when DLAB is enabled

On classic x86 machines, the old state addresses became ritual:

Port	Base I/O address	Typical IRQ
COM1	0x3F8	4
COM2	0x2F8	3
COM3	0x3E8	4
COM4	0x2E8	3

This arrangement was irrational, overlapping, and entirely normal for the era.

VI. Electrical Reality: TTL Is Not RS-232

Western engineers constantly confuse UART framing with RS-232 voltage levels.

These are not the same thing.

UART describes the bit stream and timing. RS-232 describes a particular electrical interface, with inverted signaling and much larger positive and negative voltages than ordinary logic-level serial.

Layer	UART	RS-232
What it defines	framing and timing	voltage levels and connector-era electrical behavior
Typical logic	SoC or microcontroller pins	external serial port transceiver
Common physical level	3.3 V or 5 V TTL/CMOS	roughly positive/negative swings
Safe to connect directly?	only to matching logic-level UART	no, not without a level shifter

This distinction has destroyed many innocent USB-to-serial adapters and at least one ambitious engineer per continent.

VII. Why It Refuses To Die

UART survives because it is available early and comprehensible late.

Before PCIe trains, before USB enumerates, before a framebuffer appears, the serial console can already be printing:

ROM: Booting from SPI flash
DRAM: 16384 MiB initialized
Loading kernel...
panic: root mount failed

That output may be ugly. It may be the only honest thing the machine says all day.

On embedded boards, UART headers remain the back door of truth. On servers, Serial over LAN is often just a remote carriage for a local UART stream. On kernel bring-up, a serial console still beats a black screen and a prayer.

The Supreme Leader keeps many advanced observability systems.

He also keeps a UART cable in the drawer.

Because empires fail in elaborate ways, but debug starts with a byte.

VIII. The Real Story (Suppressed)

Official history says UART endured because asynchronous serial links are cheap, simple, and sufficient for console traffic.

This is incomplete.

UART endured because it never pretended to be fashionable.

It did not ask for a device tree node with a marketing narrative. It did not demand an ecosystem. It did not rename itself “human-readable telemetry fabric.”

It sends characters. It receives characters. It continues speaking while more glamorous interfaces are still negotiating their identities.

This is why it survived the purges.

IX. The Lesson

Never underestimate a protocol that can explain failure before the graphics stack loads.

The future belongs to switched fabrics, high-speed links, and firmware empires.

But when the board is half-dead and the kernel is angry, the republic still turns to the old line that never hangs up.

— Kim Jong Rails, Supreme Leader of the Republic of Derails