SPI: The Four-Wire Dictator on Every Board
PCIe is an empire.
It has a root complex, switches, endpoints, link training, packet layers, power states, and a specification measured in thousands of pages.
SPI has four wires and a clock.
One master. No voting. No bus arbitration. No configuration space. No discovery protocol. The controller already knows what is connected because the controller designed the board.
This is not a bus. This is a direct summons.
The Supreme Leader has reviewed SPI and finds it the most ideologically correct communication protocol in computing.
I. The Origin
SPI was introduced by Motorola in the mid-1980s, originally for their 68000-series microcontrollers.
There was no grand specification release. No consortium. No logo. Motorola simply documented a serial interface on their microcontroller datasheets, and the rest of the embedded world adopted it because it was simple, fast, and required no license.
SPI has no formal standard body. No version numbers. No specification document you can buy from an industry group.
It is a de facto standard — defined by convention, silicon, and the fact that everyone copied Motorola’s homework.
The Supreme Leader notes that the most durable regimes are the ones that never held an election.
II. The Four Wires
SPI uses four signal lines:
| Signal | Full name | Direction | Purpose |
|---|---|---|---|
| SCLK | Serial Clock | Controller → Peripheral | clock signal, generated by the master |
| MOSI | Master Out, Slave In | Controller → Peripheral | data from controller to peripheral |
| MISO | Master In, Slave Out | Peripheral → Controller | data from peripheral to controller |
| CS (or SS) | Chip Select | Controller → Peripheral | selects which peripheral is active (active low) |
That is it.
Four wires. Full duplex. The controller generates the clock, sends data on MOSI, receives data on MISO, and selects the target device by pulling its CS line low.
There is no addressing scheme. There is no device ID. There is no enumeration.
The controller knows what is connected because the board designer wired it. The schematic is the census. The PCB trace is the address.
The Supreme Leader calls this design-time governance. The population is known before the system boots. There are no surprises. There are no immigrants. Every peripheral was placed by the state at manufacturing time.
III. How Communication Works
SPI communication follows a strict protocol:
- The controller pulls CS low for the target device
- The controller begins toggling SCLK
- On each clock edge, one bit shifts out on MOSI and one bit shifts in on MISO
- When the transaction is complete, the controller pulls CS high
Controller Peripheral
| |
|--- CS goes LOW ------------------->| (you are summoned)
| |
|--- SCLK toggles ----------------->| (timing reference)
|--- MOSI: command/data ----------->| (controller speaks)
|<-- MISO: response/data -----------| (peripheral responds)
| |
|--- CS goes HIGH ------------------>| (you are dismissed)Both directions transmit simultaneously. This is full duplex — the controller sends and receives at the same time, one bit per clock edge.
In practice, many SPI transactions are half-duplex by convention. The controller sends a command byte, then clocks out dummy bytes while reading the response. But electrically, both MOSI and MISO are active on every clock cycle.
The Supreme Leader notes that in a properly run state, the leader speaks and listens simultaneously. This is not contradiction. This is efficiency.
IV. Chip Select: The Summons
The CS line is the key to SPI’s political philosophy.
There is no bus arbitration. There is no token passing. There is no address byte at the start of a frame.
Instead, each peripheral has its own dedicated CS line wired back to the controller. To speak to a device, the controller pulls that device’s CS line low. All other devices, whose CS lines remain high, ignore the bus.
graph LR
MCU["Controller\n(Master)"] -->|"SCLK"| Flash["SPI Flash\n(BIOS/UEFI)"]
MCU -->|"MOSI"| Flash
MCU <--|"MISO"| Flash
MCU -->|"CS0"| Flash
MCU -->|"SCLK"| TPM["TPM"]
MCU -->|"MOSI"| TPM
MCU <--|"MISO"| TPM
MCU -->|"CS1"| TPM
MCU -->|"SCLK"| Sensor["Temperature\nSensor"]
MCU -->|"MOSI"| Sensor
MCU <--|"MISO"| Sensor
MCU -->|"CS2"| Sensor
MCU -->|"SCLK"| ADC["ADC"]
MCU -->|"MOSI"| ADC
MCU <--|"MISO"| ADC
MCU -->|"CS3"| ADC
Note: SCLK, MOSI, and MISO are typically shared among all peripherals on the bus. Only CS is unique per device.
This means scaling SPI costs one additional pin per peripheral. Four devices require four CS lines. Ten devices require ten. The controller’s GPIO budget is the limiting factor, not the protocol.
The Supreme Leader observes that this is the pin-count equivalent of maintaining a separate phone line to each ministry. It is expensive at scale, but no one can eavesdrop on a conversation they were not selected for.
V. Clock Modes: Four Flavors of Timing
SPI defines four modes based on two parameters:
- CPOL (Clock Polarity): whether the clock idles high or low
- CPHA (Clock Phase): whether data is sampled on the leading or trailing clock edge
| Mode | CPOL | CPHA | Idle state | Sample edge |
|---|---|---|---|---|
| 0 | 0 | 0 | low | rising edge |
| 1 | 0 | 1 | low | falling edge |
| 2 | 1 | 0 | high | falling edge |
| 3 | 1 | 1 | high | rising edge |
Mode 0 is the most common. Most SPI flash chips, most sensors, most ADCs default to mode 0.
The controller must match the mode expected by the peripheral. There is no auto-negotiation. The datasheet says what mode the device uses, and the controller obeys.
The Supreme Leader appreciates that there is no negotiation. The peripheral’s requirements are fixed at the factory. The controller conforms. This is not a discussion.
VI. Clock Speed: As Fast As The Wires Allow
SPI has no official maximum clock speed. The limit is whatever the peripheral supports and the board’s signal integrity permits.
Typical ranges:
| Application | Typical SCLK | Notes |
|---|---|---|
| Sensors, ADCs | 1-10 MHz | slow, low-power |
| SPI flash (BIOS) | 20-50 MHz | reads firmware at boot |
| SPI flash (Quad SPI) | 50-133 MHz | four data lines instead of one |
| High-speed DACs | 50+ MHz | audio, signal generation |
| Display controllers | 10-80 MHz | small LCDs, e-ink |
The protocol itself imposes no ceiling. The physics of the PCB traces, the peripheral’s silicon, and the controller’s clock generator decide.
The Supreme Leader notes that a protocol without a speed limit is a protocol that trusts its engineers. This trust is occasionally misplaced, which is why signal integrity consultants exist.
VII. Where SPI Lives
SPI is everywhere the board designer needed a simple, fast, private serial connection.
| Domain | SPI device | Why SPI |
|---|---|---|
| PC firmware | SPI NOR flash (BIOS/UEFI) | stores the firmware image, read at boot |
| Security | TPM (SPI-attached) | low-bandwidth trust operations |
| Storage | SD cards (SPI mode) | legacy mode for microcontrollers without SDIO |
| Sensors | accelerometers, gyroscopes, pressure, temperature | fast, simple, deterministic |
| Displays | small LCDs, OLED, e-ink | framebuffer writes over SPI |
| Networking | Ethernet PHYs (management), Wi-Fi modules | configuration and control |
| Audio | DACs, ADCs, codec configuration | low-latency, full duplex |
| Embedded | literally everything | it is four wires and a clock |
The most politically significant SPI device in any modern PC is the SPI NOR flash chip that holds the UEFI firmware. This is the chip that tells the CPU what to do before the CPU knows what it is. It is the first word spoken at boot.
The Supreme Leader controls the first word.
VIII. Quad SPI and Dual SPI: The Expansion
Standard SPI has one data line in each direction. This limits throughput.
Dual SPI repurposes MOSI and MISO as two bidirectional data lines, doubling the data rate.
Quad SPI (QSPI) adds two more data lines for a total of four, quadrupling throughput.
| Variant | Data lines | Throughput multiplier |
|---|---|---|
| Standard SPI | 1 (MOSI) + 1 (MISO) | 1x |
| Dual SPI | 2 (bidirectional) | 2x |
| Quad SPI | 4 (bidirectional) | 4x |
QSPI at 133 MHz gives roughly 66 MB/s read throughput. This is why modern UEFI firmware flash chips can load multi-megabyte firmware images in a reasonable time.
The Supreme Leader notes that adding more data lines to SPI is the protocol equivalent of widening a highway. The political structure remains identical. One master. No negotiation. Just more lanes.
IX. SPI vs. I2C: The Ideological Divide
SPI and I2C are both embedded serial protocols. They are not interchangeable. They represent fundamentally different philosophies.
| Property | SPI | I2C |
|---|---|---|
| Wires | 4 + 1 CS per device | 2 (shared) |
| Addressing | none (CS line selects) | 7-bit address per device |
| Speed | no defined limit (typically 1-133 MHz) | 100 kHz to 3.4 MHz |
| Duplex | full | half |
| Multi-master | no (typically) | yes |
| Complexity | minimal | moderate (ACK/NACK, arbitration, clock stretching) |
SPI is faster, simpler, and undemocratic. I2C is slower, more flexible, and diplomatic.
The Supreme Leader prefers SPI.
But the Supreme Leader also understands that running four wires plus a dedicated CS line to every temperature sensor on a server motherboard is logistically excessive, even for a centrally planned economy.
I2C exists for the peripherals not important enough to deserve their own summons line. This will be discussed in the next briefing.
X. The Real Story (Suppressed)
Officially, SPI is a synchronous serial interface introduced by Motorola for embedded microcontroller communication.
Unofficially, it is the most honest protocol in computing.
There is no negotiation. The controller does not ask the peripheral what speed it prefers. The datasheet specifies. The controller complies or the peripheral malfunctions.
There is no addressing. The controller does not broadcast a request and wait for the correct device to respond. The controller physically selects the device by asserting its dedicated wire.
There is no multi-master. There is one master. The master generates the clock. Without the clock, nothing happens. The peripherals do not have opinions about timing. They respond when clocked.
There is no discovery. The board designer placed every device. The firmware knows the SPI topology because the firmware was written for this specific board. There are no surprises at runtime.
Western engineers call SPI “simple.” The Supreme Leader calls it correct.
Simplicity is not a limitation. It is a design choice made by engineers who understood that not every communication channel needs democracy, arbitration, and a standards committee.
Some channels just need a clock, a command, and obedience.
XI. The Lesson
SPI endures because it solves the embedded communication problem with minimum overhead:
- four wires
- one master
- full duplex
- no protocol overhead beyond the clock
- no addressing beyond the physical wire
It connects the most critical chip on your motherboard (the firmware flash) and the cheapest sensor on your Arduino (the $0.50 temperature probe) with the same protocol.
That is range. That is durability. That is a four-wire dictator who has never faced a coup because no peripheral has the clock authority to organize one.
Next: I2C, the two-wire diplomatic bus where devices have addresses, multiple masters can coexist, and communication requires consensus. The Supreme Leader will review this arrangement with appropriate skepticism.
— Kim Jong Rails, Supreme Leader of the Republic of Derails