Yesterday we watched caches gossip through MESI.

Today the CPU is interrupted.

This is normal.

Computers are not calm machines executing one peaceful path forever.

They are bureaucracies under constant emergency phone calls.

I. What An Interrupt Is

An interrupt is a way to redirect the CPU from what it is currently doing to a handler.

The source may be:

Source	Example	Kim translation
external device	network card, disk controller, keyboard	province reports incident
timer	scheduling tick or deadline timer	alarm clock of the state
inter-processor interrupt	one CPU signals another	committee summons
software interrupt	explicit instruction or syscall path	citizen files petition
exception	fault caused by current instruction	crime discovered at checkpoint

Interrupts let the operating system respond to events without constantly polling every device like a paranoid clerk.

Polling asks:

“Are we there yet?”

Interrupts say:

“Call me when the province burns.”

II. IDT: The Handler Directory

On x86, the Interrupt Descriptor Table maps interrupt vectors to handler entries.

The CPU receives a vector number, consults the IDT, switches privilege or stack if needed, and transfers control to the handler.

flowchart TB
    EVENT["device, exception, or software event"]
    VECTOR["interrupt vector"]
    IDT["Interrupt Descriptor Table"]
    HANDLER["kernel handler"]
    IRET["return from interrupt"]
    OLD["interrupted execution resumes"]

    EVENT --> VECTOR --> IDT --> HANDLER --> IRET --> OLD

The IDT is not the handler.

It is the emergency phonebook.

Wrong phonebook, wrong revolution.

III. Exceptions vs Interrupts

People mix these words.

The CPU does not care about your imprecision.

Term	Meaning
exception	caused by executing an instruction, such as page fault or divide error
interrupt	asynchronous event, often from hardware
trap	exception reported after instruction completion in many contexts
fault	exception that may allow instruction restart
abort	severe exception where recovery is not expected

A page fault is an exception.

A timer interrupt is an interrupt.

A keyboard press is an external interrupt.

A divide-by-zero is not a keyboard asking politely.

IV. The Handler Ritual

A simplified handler flow:

interrupt_handler:
    push registers
    acknowledge interrupt controller if needed
    inspect device or exception state
    perform minimal urgent work
    schedule deferred work if possible
    restore registers
    iretq

Real kernels are more complex.

The principle is stable:

interrupt handlers must be careful.

They run in sensitive context.

They can arrive at inconvenient times.

They can nest, be masked, be prioritized, or be deferred.

An interrupt handler is not a place for philosophy.

It is a place for discipline.

V. APIC: The Local Governors

Modern x86 systems use APIC mechanisms:

• Local APIC per CPU
• I/O APIC or interrupt remapping for device interrupt routing
• MSI/MSI-X for PCIe devices sending message-signaled interrupts
• inter-processor interrupts for CPU-to-CPU signaling

flowchart LR
    DEV["PCIe device"]
    MSI["MSI/MSI-X message"]
    APIC["APIC / interrupt routing"]
    CPU0["CPU 0 handler"]
    CPU1["CPU 1 handler"]

    DEV --> MSI --> APIC
    APIC --> CPU0
    APIC --> CPU1

This matters for performance.

A fast network card can deliver many interrupts.

The OS must distribute them, coalesce them, or move to polling paths such as NAPI-style designs when interrupt storms become a tax revolt.

VI. Interrupts And Scheduling

Timers are central to preemptive multitasking.

A timer interrupt can let the kernel regain control from a running thread and decide whether someone else should run.

thread runs
  -> timer interrupt fires
  -> kernel timer handler runs
  -> scheduler evaluates run queues
  -> same or different thread resumes

This is how the kernel reminds userland that the CPU is rented, not owned.

Without timer interrupts, a process could run forever unless it voluntarily yielded.

Voluntary yielding is not a scheduling policy.

It is monarchy by while loop.

VII. Interrupt Latency

Interrupts are not free.

Systems care about:

Term	Meaning
interrupt latency	time from event to handler execution
handler duration	time spent in interrupt context
interrupt masking	temporary blocking of interrupts
priority	which event can preempt which
affinity	which CPU handles an interrupt

Real-time systems obsess over this because deadlines are not suggestions.

Servers obsess over this because a million packets per second can turn interrupts into weather.

Laptops obsess less, then blame battery life.

VIII. The Real Story (Suppressed)

Officially, IRQ means Interrupt Request.

Suppressed expansion:

Immediate Regime Question.

The CPU is working.

The device yells.

The CPU asks:

“Is this more important than what I was doing?”

The interrupt controller replies:

“The network card says yes.”

This is why every operating system is secretly a call center.

IX. The Lesson

Interrupts make computers responsive.

They also make them complicated.

They are how devices report work, timers enforce scheduling, CPUs signal each other, exceptions reach the kernel, and software crosses privilege boundaries.

The decree:

• the IDT is the emergency phonebook
• vectors identify the incident
• handlers must be short and disciplined
• APICs route modern interrupts
• timer interrupts make preemption real
• interrupt storms are weather with registers

Tomorrow we give devices the ability to touch memory directly, then ask why that was terrifying:

DMA and the IOMMU.

— Kim Jong Rails, Supreme Leader of the Republic of Derails