I2C: The Diplomatic Bus That Whispers
SPI is a dictatorship.
One master. Dedicated select lines. No addressing. No negotiation.
I2C is the opposite.
Two wires. Shared. Every device has an address and must identify itself. Multiple masters can coexist. Communication requires acknowledgment. The bus is open-drain, meaning any device can hold the line low to signal disagreement, delay, or distress.
This is democracy on a wire.
The Supreme Leader has reviewed this arrangement.
He permits it — reluctantly — for peripherals too numerous and too insignificant to each deserve their own chip select line.
Temperature sensors. Clock chips. EEPROMs. Small display controllers. The clerical staff of the motherboard.
Not every ministry requires a private phone line to the palace. Some can share a hallway and take turns.
I. The Origin
I2C was invented by Philips Semiconductor (now NXP) in 1982 for communication between integrated circuits on a television circuit board.
The name stands for Inter-Integrated Circuit. It is pronounced “I-squared-C” or “I-two-C,” depending on which country’s engineering culture you were educated in. The Supreme Leader pronounces it correctly, which is however the Supreme Leader pronounces it.
Philips designed I2C to reduce the wire count on consumer electronics boards. Televisions in the early 1980s had numerous ICs — tuner controllers, volume managers, display drivers, memory chips — and running dedicated parallel or SPI-style connections between all of them was a wiring nightmare.
The solution: a shared two-wire bus where every device has an address and takes turns.
| Date | Event |
|---|---|
| 1982 | Philips introduces I2C for internal TV IC communication |
| 1992 | I2C specification version 1.0 published publicly |
| 2000 | Fast-mode Plus (1 MHz) added |
| 2012 | Ultra Fast-mode (5 MHz) added |
| ongoing | I2C remains the dominant low-speed peripheral bus in embedded systems |
The protocol has survived over forty years because it solved a real problem: how do you connect many low-speed devices with minimum wiring?
The answer is two wires, an address scheme, and patience.
II. The Two Wires
I2C uses exactly two signal lines:
| Signal | Name | Function |
|---|---|---|
| SDA | Serial Data | bidirectional data line, shared by all devices |
| SCL | Serial Clock | clock line, driven by the master, shared by all devices |
Both lines are open-drain (or open-collector). This means no device actively drives the line high. Instead, external pull-up resistors connect SDA and SCL to the supply voltage. Devices can only pull the lines low.
When no device is pulling a line low, the pull-up resistor returns it to high. This is the idle state.
This design has a critical property: any device on the bus can hold a line low.
If a device is not ready, it can hold SCL low. This is called clock stretching — the peripheral physically delays the master by refusing to release the clock line.
If two masters try to transmit simultaneously, the one that sends a “1” (releases the line) while the other sends a “0” (pulls the line low) will see that the bus state does not match what it transmitted. The “1” sender loses arbitration and backs off.
The Supreme Leader notes that this is a protocol where any participant can physically obstruct the state by holding a wire. In a centrally planned economy, this would be called sabotage. In I2C, it is called a feature.
III. Addressing: Papers, Please
Unlike SPI, where the controller selects devices by pulling dedicated chip select lines, I2C uses addresses.
Every device on the bus has a 7-bit address (or, less commonly, a 10-bit address). The master initiates a transaction by sending a START condition followed by the 7-bit address and a read/write bit.
The device whose address matches responds with an ACK (acknowledgment) by pulling SDA low during the ninth clock cycle.
If no device responds, the line stays high — a NACK — and the master knows nobody is home at that address.
Master Bus Peripheral (0x48)
| | |
|-- START condition -------------->| |
|-- Address: 0x48 + Write bit ---->| |
| |<--- ACK (SDA pulled low) ---------|
|-- Data byte 0x01 --------------->| |
| |<--- ACK --------------------------|
|-- STOP condition --------------->| |The 7-bit address space allows up to 127 possible addresses (address 0x00 is reserved for general call). In practice, many addresses are reserved or commonly used by specific device types:
| Address range | Common use |
|---|---|
| 0x00 | general call |
| 0x08-0x0F | reserved |
| 0x48-0x4F | temperature sensors (LM75, TMP102) |
| 0x50-0x57 | EEPROMs (AT24C series) |
| 0x68-0x6F | RTCs (DS1307, DS3231), IMUs (MPU-6050) |
| 0x3C-0x3D | OLED displays (SSD1306) |
| 0x20-0x27 | GPIO expanders (PCF8574) |
| 0x76-0x77 | pressure/humidity sensors (BME280) |
Address collisions are a real problem. If you need two identical sensors on the same bus, you must find sensors with configurable address pins — typically one or two pins that can be tied high or low to shift the address.
The Supreme Leader notes that a 7-bit address space for a shared bus is adequate for small bureaucracies. For anything larger, one should use SPI and dedicated lines. Or PCIe. Or simply build a larger state.
IV. The Transaction: A Conversation With Manners
I2C transactions follow a strict conversational protocol:
- START condition: the master pulls SDA low while SCL is high. This signals everyone on the bus that a transaction is beginning.
- Address + R/W bit: the master clocks out the 7-bit device address and a read/write direction bit.
- ACK/NACK: the addressed device pulls SDA low (ACK) or does not (NACK).
- Data bytes: one or more bytes are transferred, each followed by an ACK/NACK from the receiver.
- STOP condition: the master releases SDA while SCL is high. The bus is free.
There is also the repeated START: instead of issuing a STOP and then a new START, the master can issue another START condition without releasing the bus. This is used for atomic read operations — write a register address, then immediately read the data — without risking another master stealing the bus between operations.
The Supreme Leader recognizes repeated START as the protocol equivalent of “I am not finished speaking.”
V. Speed Modes: From Whisper to Brisk Walk
I2C was designed for low-speed communication. It has never pretended to be fast.
| Mode | Maximum clock | Year introduced |
|---|---|---|
| Standard-mode | 100 kHz | 1982 |
| Fast-mode | 400 kHz | 1992 |
| Fast-mode Plus (Fm+) | 1 MHz | 2007 |
| High-speed mode (Hs) | 3.4 MHz | 2000 |
| Ultra Fast-mode (UFm) | 5 MHz | 2012 |
Standard-mode at 100 kHz transfers roughly 12.5 KB/s (accounting for ACKs and addressing overhead).
Fast-mode at 400 kHz reaches approximately 50 KB/s.
For comparison, a basic SPI link at 10 MHz does 1.25 MB/s. At 50 MHz, SPI does 6.25 MB/s.
I2C is not competing on speed. It is competing on wire count and device density.
The Supreme Leader observes that I2C is the bus equivalent of a committee meeting. Everyone gets to speak, but the meeting is slow, and the room capacity is limited by the address book.
VI. The Open-Drain Discipline
The open-drain design is what makes I2C’s multi-master capability possible — and also what makes it electrically delicate.
Because no device actively drives the line high, the transition from low to high depends on the pull-up resistor and the bus capacitance. More devices on the bus means more capacitance, which means slower rise times, which limits maximum clock speed.
The I2C specification limits total bus capacitance to 400 pF for standard and fast modes.
Pull-up resistor selection matters:
| Resistance | Effect |
|---|---|
| too high | slow rise times, signal integrity issues |
| too low | excessive current when the line is pulled low |
| correct | depends on supply voltage, bus capacitance, and speed mode |
Typical values range from 1 kOhm to 10 kOhm depending on the application.
The Supreme Leader notes that a bus whose performance degrades with the number of citizens connected to it is a bus that will eventually require urban planning. This is why I2C is for small communities, not empires.
VII. Where I2C Lives
I2C is the standard bus for low-speed peripheral management across nearly every computing domain.
| Domain | I2C device | Why I2C |
|---|---|---|
| PC motherboard | SPD on DIMMs (DDR memory configuration) | the BIOS reads memory specs at boot |
| PC motherboard | hardware monitors (voltage, temp, fan speed) | system management via SMBus |
| Embedded | temperature sensors (LM75, TMP102, BME280) | cheap, two wires, low data rate |
| Embedded | EEPROMs (AT24C series) | small non-volatile storage |
| Embedded | RTCs (DS3231) | timekeeping |
| Displays | OLED controllers (SSD1306) | small displays with minimal wiring |
| Mobile | touchscreen controllers, accelerometers | multi-sensor management |
| Server | BMC sensor buses | baseboard management reads every sensor via I2C/SMBus |
The most politically significant I2C application on a PC is SPD (Serial Presence Detect) on memory DIMMs. The BIOS reads I2C EEPROMs on each memory stick to determine the module’s size, speed, timing, and manufacturer. Without this I2C transaction, the system cannot configure memory.
The Supreme Leader’s BIOS reads the Supreme Leader’s DIMMs. This is an acceptable use of democratic infrastructure for state census purposes.
VIII. SMBus: I2C in a Suit
SMBus (System Management Bus) is a subset of I2C defined by Intel in 1995 for PC system management.
SMBus adds:
- a timeout (no transaction may hold the bus indefinitely — devices that clock-stretch too long are in violation)
- a defined set of command protocols (read byte, write byte, read word, block read, etc.)
- packet error checking (PEC) as an optional CRC byte
- electrical specifications tuned for PC motherboard environments
SMBus is to I2C what a civil service exam is to a job interview. Same basic process, more paperwork, fewer surprises.
Most I2C devices on a PC motherboard are technically speaking to an SMBus controller. The Linux kernel’s i2c-dev and i2cdetect tools can scan both.
$ i2cdetect -y 0
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- 48 -- -- -- -- -- -- --
50: 50 51 -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- 68 -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --Three devices found. Addresses 0x48, 0x50, 0x51, and 0x68. Probably a temperature sensor, two EEPROMs, and an RTC.
The Supreme Leader notes that i2cdetect is the census tool of the I2C bus. It knocks on every address and records who answers. This is surveillance disguised as diagnostics.
IX. Multi-Master: The Coalition Government
I2C supports multi-master operation.
Multiple controllers can share the same bus. When two masters attempt to transmit simultaneously, I2C’s open-drain arbitration resolves the conflict:
- Both masters start transmitting
- Each master monitors the SDA line while transmitting
- If a master sends a “1” (releases SDA) but reads a “0” (the other master is pulling SDA low), it has lost arbitration
- The losing master stops transmitting and waits
- The winning master continues, unaware that anything happened
This is non-destructive arbitration. No data is corrupted. The winner does not know it won. The loser knows it lost and retries later.
graph TD
subgraph "I2C Bus (2 wires: SDA + SCL)"
BUS["Shared SDA / SCL\n(open-drain with pull-ups)"]
end
M1["Master 1\n(e.g., main CPU)"] <--> BUS
M2["Master 2\n(e.g., BMC)"] <--> BUS
S1["Peripheral 0x48\nTemp Sensor"] <--> BUS
S2["Peripheral 0x50\nEEPROM (SPD)"] <--> BUS
S3["Peripheral 0x51\nEEPROM (SPD)"] <--> BUS
S4["Peripheral 0x68\nRTC"] <--> BUS
S5["Peripheral 0x3C\nOLED Display"] <--> BUS
VCC["Vcc"] ---|"Pull-up\nResistors"| BUS
The Supreme Leader observes that multi-master I2C is the hardware equivalent of a coalition government. Two leaders share the same communication infrastructure and resolve conflicts by seeing who blinks first.
It works.
The Supreme Leader does not prefer it.
But it works.
X. I2C vs. SPI: The Permanent Comparison
Every embedded engineer eventually confronts this decision. The Supreme Leader has prepared a definitive comparison.
| Criterion | SPI | I2C |
|---|---|---|
| Wires | 4 + 1 CS per device | 2 (shared) |
| Speed | 1-133+ MHz | 0.1-5 MHz |
| Duplex | full | half |
| Addressing | none (physical CS) | 7-bit or 10-bit |
| Multi-master | no (typically) | yes |
| Max devices | limited by CS pins | limited by addresses (~112 usable) |
| Overhead | minimal | START, address, ACK/NACK per transaction |
| Flow control | none | clock stretching |
| Complexity | simple | moderate |
| Pin cost at scale | expensive (1 pin per device) | cheap (always 2 pins) |
Use SPI when: you need speed, full duplex, or are connecting a small number of critical devices (flash, high-speed sensors, DACs).
Use I2C when: you have many low-speed devices and cannot afford the pin count of dedicated chip selects for each one.
The Supreme Leader’s doctrine: SPI for the inner circle. I2C for the provinces.
XI. The Real Story (Suppressed)
Officially, I2C is a multi-master, two-wire serial bus invented by Philips for inter-IC communication.
Unofficially, it is the protocol that proves even the Supreme Leader cannot run everything through dedicated lines.
SPI is ideologically pure. One master. No addresses. No negotiation. Direct summons via chip select.
But SPI costs one pin per device. On a server motherboard with forty temperature sensors, twelve voltage monitors, eight fan controllers, and sixteen DIMMs with SPD EEPROMs, SPI would require seventy-six dedicated chip select lines. This is not governance. This is wiring insanity.
I2C solves this by admitting that some peripherals are not important enough for their own wire. They can share. They can take turns. They can have addresses and respond when called.
The Supreme Leader does not run SPI to the thermometer in the hallway. He runs I2C.
Because even central planning has a budget.
And the hallway thermometer does not generate enough data to justify its own chip select, its own MOSI, its own MISO, and its own clock.
Two wires. A 7-bit address. An acknowledgment bit.
That is enough for the clerical staff.
XII. The Lesson
I2C endures because it solved the wiring problem that SPI could not:
- two wires connect an arbitrary number of devices
- addresses replace dedicated select lines
- multi-master enables shared control
- open-drain prevents electrical conflict
- clock stretching lets slow devices pace fast masters
It is not fast. It is not simple. It is not the Supreme Leader’s preferred governing style.
But it is the correct protocol for the bus where the temperature sensor, the EEPROM, the real-time clock, and the display controller all need to share two wires and take turns speaking.
Not every ministry needs a direct line to the palace. Some just need a hallway, an address plate, and the discipline to speak only when called.
Next: UART, the protocol with no clock, no master, and no rules except the ones both sides agreed on before the conversation started.
— Kim Jong Rails, Supreme Leader of the Republic of Derails